CS89712 Datasheet, PDF (140/170 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH 10BASE-T ETHERNET CONTROLLER

CS89712
5. MECHANICAL INFORMATION
5.1 256-PBGA PIN DIAGRAM
16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
TXDN N/C N/C RXDP RXDN RES VssA XTAL XTAL EECS EE Vss DD
SD
CS
A
TXDP
1
2
DOUT I/O
3 CS0 0
VddA VssA Vss VssA VddA VssA VddA LINK LAN VssA EESK EE N/C DD SDQM CS
B
I/O
LED LED
DIN
2
3
1
D
D
D
Vss
D
Vdd N/C N/C Vss N/C N/C Vdd CL DD SDQM CS
C
3
4
5
I/O
6
I/O
I/O
I/O
1
1
2
3
MOE/ Vdd Vss D N/C A
SDCAS I/O
I/O
2
19
D N/C D
0
15
D
N/C Vdd FRM DD
SD
CS
D
13
CORE
0 CKE 4
A
A
D
A
A
A MWE/ D
Vss
D
Vdd CL
M
SD SD EXP _E
16
15
1
18
6
17 ^SDWE 12
I/O
10
I/O
2
CS1 CLK CLK
A
A
Vss Vss
A
14
13
I/O I/O
4
A WAKE PWR Vdd
5
UP FL I/O
D Vss Vss Vdd Vss
11 CORE I/O I/O I/O
CS WORD _F
5
A VDD A
12 I/O 11
A ETH Vss Vdd MOSC Vss Vss Vss TXD TDI EXP Vdd WRITE _G
3 ENBL I/O OSC IN OSC I/O I/O
2
RDY I/O
A
A
10
9
A
ETH uRST Vss Vss MOSC PA
PA
PB
PB
PB RXD Vss RUN _H
7 ENBL
I/O I/O OUT 4
6
6
5
1
2
I/O
N/C A
A
D nMED D
Vss TEST PE LED Vdd PA TDO PB PB0/ PB
J
2
1
7 CHG 8
I/O
1
2 DRV I/O
3
4 PRDY1 7
N/C
A
N/C nBAT A
Vdd SSI SSI PD
PD TEST PA PHD PA
PB
PB
K
0
CHG 8
I/O TXDA TXFR 1
2
0
1
IN
5
2
3
Vdd Vdd BAT VSS D
D
Vss DRV SSI DRV PD PE TXD CTS PA PA
L
I/O I/O OK I/O
9
14 I/O
0 RXFR 1
3
0
1
2
7
nPOR nTRST Vss nEXT D COL Vdd FB ADC Vss Vdd PE RXD Vss DSR PA
M
I/O PWR 17
6
I/O
0 CLK I/O I/O
1
1
I/O
0
D
D
D
D Vdd COL COL COL COL SMP ADC PD nEXT N/C nEINT DCD _N
18
21
16
19
I/O
1
0
2
7 CLK CS
5
FIQ
1
A
A
D
D
A
D
Vss
D
COL FB Vdd SSI PD6/ Vdd Vss nEINT _P
20
23
20
22
22
28
I/O
31
3
1
I/O RXDA SDQM0 RTC RTC
2
D
D
A Vss Vdd Vss A
D BUZ COL Vdd ADC PD PD RTC RTC _R
23
24
21
I/O I/O I/O
27
30
4
I/O IN
0
4 OUT IN
A24 HALF D
A
D
A
D
D TCLK COL ADC Vdd Vss SSI TMS PD7/ _T
WORD 25
25
26
26
27
29
5 OUT I/O I/O CLK
SDQM1
Table 89. 256-Ball PBGA Ball Listing (bottom view)
140
DS502PP2