EP7309 Datasheet, PDF (4/46 Pages) Cirrus Logic – HIGH PERFORMANCE LOW POWER SYSTEM ON CHIP ENHANCED DIGITAL AUDIO INTERFACE

EP7309
High-Performance, Low-Power System on Chip
Universal Asynchronous
Receiver/Transmitters (UARTs)
The EP7309 includes two 16550-type UARTs for RS-232
serial communications, both of which have two 16-byte
FIFOs for receiving and transmitting data. The UARTs
support bit rates up to 115.2 kbps. An IrDA SIR protocol
encoder/decoder can be optionally switched into the
RX/TX signals to/from UART 1 to enable these signals
to drive an infrared communication interface directly.
Pin Mnemonic
I/O
Pin Description
TXD[1]
RXD[1]
CTS
DCD
DSR
TXD[2]
RXD[2]
LEDDRV
PHDIN
O
UART 1 transmit
I
UART 1 receive
I
UART 1 clear to send
I
UART 1 data carrier detect
I
UART 1 data set ready
O
UART 2 transmit
I
UART 2 receive
O
Infrared LED drive output
I
Photo diode input
Table C. Universal Asynchronous Receiver/Transmitters Pin
Assignments
Digital Audio Interface (DAI)
The EP7309 integrates an interface to enable a direct
connection to many low cost, low power, high quality
audio converters. In particular, the DAI can directly
interface with the Crystal^‚ CS43L41/42/43 low-power
audio DACs and the Crystal^‚ CS53L32 low-power ADC.
Some of these devices feature digital bass and treble
boost, digital volume control and compressor-limiter
functions.
Pin Mnemonic
I/O
Pin Description
SCLK
SDOUT
SDIN
LRCK
MCLKIN
MCLKOUT
O Serial bit clock
O Serial data out
I
Serial data in
O Sample clock
I
Master clock input
O Master clock output
Table D. DAI Interface Pin Assignments
CODEC Interface
The EP7309 includes an interface to telephony-type
CODECs for easy integration into voice-over-IP and
other voice communications systems. The CODEC
interface is multiplexed to the same pins as the DAI and
SSI2.
Pin Mnemonic
I/O
Pin Description
PCMCLK
PCMOUT
PCMIN
PCMSYNC
O
Serial bit clock
O
Serial data out
I
Serial data in
O
Frame sync
Table E. CODEC Interface Pin Assignments
Note: See Table Q on page 7 for information on pin
multiplexes.
SSI2 Interface
An additional SPI/Microwire1-compatible interface is
available for both master and slave mode
communications. The SSI2 unit shares the same pins as
the DAI and CODEC interfaces through a multiplexer.
• Synchronous clock speeds of up to 512 kHz
• Separate 16 entry TX and RX half-word wide FIFOs
• Half empty/full interrupts for FIFOs
• Separate RX and TX frame sync signals for
asymmetric traffic
Pin Mnemonic
I/O
Pin Description
SSICLK
SSITXDA
SSIRXDA
SSITXFR
SSIRXFR
I/O Serial bit clock
O
Serial data out
I
Serial data in
I/O Transmit frame sync
I/O Receive frame sync
Table F. SSI2 Interface Pin Assignments
Note: See Table Q on page 7 for information on pin
multiplexes.
Note: See Table Q on page 7 for information on pin
multiplexes.
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