AZT70 Datasheet, PDF (8/12 Pages) Arizona Microtek, Inc – Programmable Capacitive Tuning IC

Arizona Microtek, Inc.
AZT70
Programmable Capacitive Tuning IC
bit 0
bit 1
DA
bit0
loaded 1^st
bit 2
bit 3
bit 4
bit 5
bit 6
bit5
selected
bit 7
bit 8
bit 9 bit 10
bit10
loaded last
CLK
≥ 0.6*V_DD
PV
≤ 0.4V
With an external 68kΩ resistor pull-up to V_DD
indeterminate
Figure 10 – Timing diagram to read bits from EEPROM
Resulting voltage if
bit5 was high in
EEPROM
Resulting voltage if
bit5 was low in
EEPROM
t
ERASING THE EEPROM
The EEPROM can be erased by initiating a programming cycle with all DA bits set high, including bit9 and bit10. After
the programming cycle, all the EEPROM bits are set low (logical high) except for the check bit (bit0), which remains
high.
Table 5 – Erase sequence for EEPROM
Step
1
Set the V_DD supply voltage to +5.0V
Action
2
Load the programming word bits all high.
3
Set the PV pin to +6V (≥5.6V, ≤6.1V) with the pulse and idle shown in timing diagram (Figure 11)
4
Verify the correct EEPROM contents by reading back the individual bits
bit 0
bit 1
DA
bit0
loaded 1^st
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 8
bit 9 bit 10
bit10
loaded last
EEPROM has
been erased
(no capacitors
selected)
CLK
PV
10ms
min
4µs
min
≥5.6V,
≤6.1V
t
Figure 11 – Programming Sequence for erasing the EEPROM
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May 2012, Rev 1.2