AZT70 Datasheet, PDF (7/12 Pages) Arizona Microtek, Inc – Programmable Capacitive Tuning IC

Arizona Microtek, Inc.
AZT70
Programmable Capacitive Tuning IC
bit 0
bit 1
DA
bit 0
loaded 1^st
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 8
bit 9 bit 10
bit 10
loaded last
CLK
PV
10ms
min
4µs
min
≥5.6V,
≤6.1V
t
Figure 8 – First programming cycle to program bit2 into the EEPROM
bit 0
bit 1
DA
bit 0
loaded 1^st
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 8
bit 9 bit 10
bit 10
loaded last
CLK
PV
10ms
min
4µs
min
≥5.6V,
≤6.1V
t
Figure 9 – Second programming cycle to program bit4 into the EEPROM
READING BACK FROM THE EEPROM
During programming, the PV pin is used to program the necessary control bits into the EEPROM. However, it is also used
to read the bits currently programmed into the EEPROM. When the PV pin is not used during programming, the AZT70
provides a weak pull-up and pull-down on the pin. This allows the EEPROM data to be shifted out to the PV pin and read
after the CLK sequence is complete and when the DA & CLK pins are high (Figure 10). Each EEPROM bit is selected by
setting the DA signal low (EEPROM selection is active low) during the CLK sequence. With an external 68kΩ resistor
pull-up to V_DD on the PV pin, a low EEPROM bit produces ≤ 0.4V level while a high EEPROM bit produces a ≥ 0.6*V_DD
level.
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May 2012, Rev 1.2