AZT70 Datasheet, PDF (2/12 Pages) Arizona Microtek, Inc – Programmable Capacitive Tuning IC

Arizona Microtek, Inc.
AZT70
Programmable Capacitive Tuning IC
PIN DESCRIPTION AND CONFIGURATION
Table 1 - Pin Description
Pin Name Type
1
X₁
Output
2
NC
n/a
3
V_SS
Power
4
V_DD Power
5
DA Input
6
CLK Input
7
NC
n/a
8
PV
Input
Function
Capacitance
not connected
Negative Supply (GND)
Positive Supply
Programming Data Input
Programming Clock Input
not connected
Programming Voltage
X₁
1
NC 2
V_SS
3
V_DD
4
8 _PV
7 _NC
6 _CLK
5 _DA
ENGINEERING NOTES
Figure 1 – Pin Configuration
CAPACITOR STRUCTURE
The AZT70 capacitance value is composed of three parallel capacitor banks, C_F is a fixed capacitor value of 2.8pF and
C_mid & C_lo are variable capacitors of differing ranges and resolutions as seen in Table 2. Capacitors composing C_mid and
C_lo are set with a binary control word through an 11-bit shift register described in PROGRAMMING the AZT70. The
values of each C_lo and C_mid stepping are detailed in the complete Nominal Capacitance Binary Mapping spreadsheet.
C_Total = C_F + C_mid + C_lo
Table 2 - AZT70 Capacitor Structure
Internal
Capacitor
C_F
C_mid
C_lo
Total
Min Value
(pF)
2.8
0
0
2.8
Max Value
(pF)
2.8
9.8
1.953
14.553
Step Size
(pF)
n/a
1.4
0.063
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May 2012, Rev 1.2