AZT70 Datasheet, PDF (5/12 Pages) Arizona Microtek, Inc – Programmable Capacitive Tuning IC

Arizona Microtek, Inc.
AZT70
Programmable Capacitive Tuning IC
PROGRAMMING MODES
The AZT70 has two capacitance setting modes from which bits are set and the matching capacitors are selected.
• Reading directly from the shift register
o This is useful for testing the capacitance and subsequent oscillator frequency. This mode is active after
the last bit is shifted in and when the CLK pin is left logic high. For the shift register, capacitors are
selected when bits are active HIGH.
• Reading from the value contained in the EEPROM
o Prevents customer adjustment and retains factory programming and is active when the CLK pin is at logic
low or not connected. For the EEPROM, capacitors are selected when bits are active LOW.
PROGRAMMING FROM THE SHIFT REGISTER
To initially determine the capacitance value for the desired center frequency of the oscillator one should set the
capacitance of the AZT70 directly from the active shift register bits. To accomplish this, the CLK pin is left high after the
last control word bit has been shifted in. Figure 5 shows the control word 11001100100 has been serially entered into the
register. Note that bit0 is the 1^st bit to enter and bit10 is the last. In the AZT70, bit0, bit9 & bit10 do not affect the
capacitance value but still must be included in the serial bit stream. For the shift register, capacitors are selected when bits
are active HIGH.
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 8
bit 9 bit 10
DA
bit 0
loaded 1^st
Register data
active when
CLK is high
CLK
t
Figure 5 - Shift register programming
WRITING DATA TO THE EEPROM
Once the desired capacitance value has been determined, the digital control word can be written or re-written into the
EEPROM. By storing the control word in the EEPROM, the customer is prevented from making adjustments from the
factory set programming data. This is accomplished within the AZT70 with internal pull-downs on the DA, PV, and CLK
pins. The detailed sequence for writing data to the EEPROM within the AZT70 is described in Table 4. Note that with
EEPROM, capacitors are selected when bits are active LOW.
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May 2012, Rev 1.2