AZP53_13 Datasheet, PDF (7/13 Pages) Arizona Microtek, Inc – Low Phase Noise Sine Wave / CMOS to LVPECL Buffer / Translator

Arizona Microtek, Inc.
EVALUATION BOARD (EBP53)
AZP53
Low Phase Noise Sine Wave/CMOS
to LVPECL Buffer/Translator
Arizona Microtek’s evaluation board EBP53 provides the most convenient way to test and prototype AZP53 series
circuits. Built for the AZP53Q 1.5x1.0 mm package, it is designed to support both dual and single supply operation. Dual
supply operation (V_DD=+2.0V, V_SS=-1.3V) enables direct coupling to 50Ω time domain test equipment (Figure 7).
Output
Stage
V_bp ^M1
V_DD (+2.0 V)
M2
21.1mA
21.1mA
Test
Equipment
Terminations
Q
Q
21.1mA - High
D
M3
M4 _{5.1mA - Low}
50Ω
50Ω
V_bn
M5
16mA
V_SS (-1.3 V)
Figure 7 - Split Supply LVPECL Output Termination
AC TERMINATION
Clock applications or phase noise/frequency domain testing scenarios typically require AC coupling. Figure 8 below
shows the AC coupling technique. The 200Ω resistors form the required DC loads, and the 50Ω resistors provide the AC
termination. The parallel combination of the 200Ω and 50Ω resistors results in a net 40Ω AC load termination. In many
cases this will work well. If necessary, the 50Ω resistors can be increased to about 56Ω. Alternately, bias tees combined
with current setting resistors will eliminate the lowered AC load impedance. The 50Ω resistors are typically connected to
ground but can be connected to the bias level needed by the succeeding stage.
www.azmicrotek.com
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Mar 2013, Rev 2.2