AZP53_13 Datasheet, PDF (2/13 Pages) Arizona Microtek, Inc – Low Phase Noise Sine Wave / CMOS to LVPECL Buffer / Translator

Arizona Microtek, Inc.
AZP53
PIN DESCRIPTION AND CONFIGURATION
Low Phase Noise Sine Wave/CMOS
to LVPECL Buffer/Translator
Table 1 - Pin Description
Pin
Name Type
1
Q
Output
2
Q
Output
3
EN
Input
4
GND Power
5
D
Input
6
EN_SEL Input
7 DIV_SEL Input
8
V_DD
Power
Function
LVPECL Output
LVPECL Output
Enable
Negative Supply
Sine or CMOS Input
Enable Select
Divide Select
Positive Supply
V_DD
8
Q1
7 DIV_SEL
Q1
D3
Q2
6 EN_SEL
<Date Code>
Q2
EN 3
EN 3
4
GND
5D
GND 4
Figure 1 - Pin Configuration for QFN8 & SON8, respectively
8 V_DD
7 DIV_SEL
6 EN_SEL
5D
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Mar 2013, Rev 2.2