AZP53_13 Datasheet, PDF (4/13 Pages) Arizona Microtek, Inc – Low Phase Noise Sine Wave / CMOS to LVPECL Buffer / Translator

Arizona Microtek, Inc.
AZP53
Low Phase Noise Sine Wave/CMOS
to LVPECL Buffer/Translator
Figure 2- S11, Parameters, D Input
INPUT TERMINATION
The D input bias is V_DD/2 fed through an internal 10kΩ resistor. For clock applications, an input signal of at least
750mV_pp ensures the AZP53 meets AC specifications. The input should also be AC coupled to maintain a 50% duty cycle
on the outputs. The input can be driven to any voltage between 0V and V_DD without damage or waveform degradation.
Input signal
D
A/R
10kΩ
V_DD/2
Figure 3 - Input Termination
www.azmicrotek.com
[phone]
4
Request a Sample
Mar 2013, Rev 2.2