AZP94_1205 Datasheet, PDF (5/9 Pages) Arizona Microtek, Inc – PECL/ECL ÷1, ÷2 Clock Generation Chip with Tristate Compatible Outputs

Arizona Microtek, Inc.
AZP94
D
EN
(CMOS)
Q
PECL/ECL ÷1, ÷2 Clock Generation Chip
with Tristate Compatible Outputs
Q
Figure 3 - Timing Diagram
Figure 4 illustrates the timing sequences for the AZP94 in the ÷2 mode which is determined by connecting the DIV-SEL
to V_EE. It also illustrates the enable in the active Low mode being controlled by a PECL signal. This mode is determined
by connecting the EN-SEL to V_EE via 20kΩ resistor.
D
EN
(PECL)
Q
Q
Figure 4 - Timing Diagram
1000
900
800
700
600
500
400
300
200
0
÷2
÷1
1000
2000
3000
4000
5000
6000
Input Frequency (MHz)
Figure 5 - Typical Large Signal Output Swing
Measured with 750mv D input, Q/Q¯ each terminated to V_CC-2V via 50 Ω resistors
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May 2012, Rev 2.0