AZP94_1205 Datasheet, PDF (4/9 Pages) Arizona Microtek, Inc – PECL/ECL ÷1, ÷2 Clock Generation Chip with Tristate Compatible Outputs

Arizona Microtek, Inc.
AZP94
PECL/ECL ÷1, ÷2 Clock Generation Chip
with Tristate Compatible Outputs
V_CC
Internal
Drive
L
L
H
L
DISABLED
H
H
L
L
ENABLED
Q,Q
AZP94 Transistor
Output Stage
H
L
L
L
DISABLED
Figure 2 - Typical Tristate Operation
H
Q
L
Q
V_T
Table 2 - Divide Truth Table
DIV-SEL
÷Ratio
NC
÷1
V_EE1
÷2
1 _{DIV-SEL connection must be ≤1Ω.}
EN-SEL
NC
V_EE
20kΩ to V_EE
Table 3 - Enable Truth Table
EN
Q
CMOS Low or V_EE
Low
CMOS High, V_CC or NC
Data
CMOS Low, V_EE or NC
Low
CMOS High or V_CC
Data
PECL Low, V_EE or NC
Low
PECL High or V_CC
Data
Q¯
Low
Data
Low
Data
Low
Data
Figure 3 illustrates the timing sequences for the AZP94 in the ÷1 mode which is determined by leaving the DIV-SEL open
(NC). It also illustrates the enable in the active High mode being controlled by a CMOS signal. This mode is determined
by leaving the EN-SEL open (NC).
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May 2012, Rev 2.0