AZP94_1205 Datasheet, PDF (1/9 Pages) Arizona Microtek, Inc – PECL/ECL ÷1, ÷2 Clock Generation Chip with Tristate Compatible Outputs

AZP94
PECL/ECL ÷1, ÷2 Clock Generation
Chip with Tristate Compatible Outputs
DESCRIPTION
The AZP94 is a ÷1 or ÷2 clock generation part specifically designed to
accommodate Colpitts or Pierce based oscillators. The tristate compatible
outputs allow for on-the-fly switching of multiple oscillators on a common
bus. Other features are incorporated to reduce board components. A voltage
reference and input biasing allows for easy oscillator interface.
The AZP94 provides a ÷ 2 mode of operation for more frequency options
and is selectable with a single connection. A selectable enable is also
provided which doubles as a reset when the AZP94 is in ÷2 mode. With a
single connection, the enable can be selected to operate as active high or
active low.
BLOCK DIAGRAM
www.azmicrotek.com
FEATURES
• Selectable Divide Ratio
• Selectable Enable Polarity and
Threshold (CMOS or PECL)
• Tristate Compatible Outputs
• Input Buffer Powers Down
when Disabled
• High Bandwidth
o 1.5+ GHz (÷1)
o 3.0+ GHz (÷2)
• -145 dBc/Hz (÷1) Typical
Noise Floor
• -151 dBc/Hz (÷2) Typical
Noise Floor
APPLICATIONS
• Colpitts or Pierce based
oscillators
• Multiple oscillators on a
common bus
PACKAGE AVAILABILITY
• MLP8
o Green/RoHS Compliant/Pb-Free
Part Number (PN)
Package
Marking
AZP94NAG¹
MLP8
J4G <Date Code>²
1 _{Tape & Reel - Add 'R1' at end of PN for 7in (1k parts), 'R2' (2.5k) for 13in}
2 _{See www.azmicrotek.com for date code format}
www.azmicrotek.com
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1630 S Stapley Dr, Suite 127
Mesa, AZ 85204 USA
May 2012, Rev 2.0