AZP94_1205 Datasheet, PDF (3/9 Pages) Arizona Microtek, Inc – PECL/ECL ÷1, ÷2 Clock Generation Chip with Tristate Compatible Outputs

Arizona Microtek, Inc.
ENGINEERING NOTES
AZP94
PECL/ECL ÷1, ÷2 Clock Generation Chip
with Tristate Compatible Outputs
FUNCTIONALITY
The AZP94 is a specialized ÷1 or ÷2 clock generation part including an enable/reset function. The divide ratio is selected
with the DIV-SEL pin/pad. When DIV-SEL is open (NC), the AZP94 functions as a standard receiver. If DIV-SEL is
connected to V_EE, it functions as a ÷2 divider.
Enable (EN) functionality is selected with the EN-SEL pin/pad which has three valid states: open (NC), V_EE, or connected
to V_EE via a 20kΩ ± 20% resistor. Leaving EN-SEL open or connecting it to V_EE allows the EN pin/pad to function as an
active high CMOS/TTL enable. When EN-SEL is open, an internal 75kΩ pull-up resistor is selected which enables the
outputs whenever EN is left open. When EN-SEL is connected to V_EE, an internal 75kΩ pull-down resistor is selected
which disables the outputs whenever EN is left open.
Connecting the EN-SEL to V_EE with a 20kΩ resistor will allow the EN pin/pad to function as an active low PECL/ECL
enable with an internal 75kΩ pull-down resistor. In this mode, outputs are enabled when EN is left open (NC). The default
logic condition can be overridden by connecting the EN to V_CC with an external resistor of ≤20kΩ. If the enable signal is
CMOS (rail-to-rail) and the logic sense is active low (EN-SEL connected to V_EE with a 20kΩ resistor), the EN pin/pad
voltage swing must be reduced using two external resistors. Contact the factory for details.
When the AZP94 is disabled, the Q and Q¯ outputs are forced LOW and the input buffer is powered down to minimize
feed through. This feature allows tristate compatible parallel output connections. Multiple AZP94 chip outputs can be
wired together. Since both outputs are forced LOW in the disable mode, an enabled AZP94 can drive the output lines
without interference from the unselected units. In addition, the AZP94 can be used in parallel connection with PECL/ECL
parts whose outputs are high impedance when disabled.
The EN pin/pad also functions as a reset when the ÷2 mode is selected. In the ÷2 mode, the counter resets when the
outputs are disabled.
The AZP94 provides a V_BB with an 1880Ω internal bias resistor from D to V_BB. This feature allows AC coupling with
minimal external components. The V_BB pin supports 1.5mA sink/source current and should be bypassed to ground or V_CC
with a 0.01 µF capacitor.
TRISTATE COMPATIBLE OPERATION
The outputs of the AZP94 are emitter followers as shown in the left side of Figure 2. When a part is disabled, both outputs
are set in the LOW state. This allows a HIGH output from an enabled part to override a disabled output and pull the
combined line HIGH as seen in the right hand side of Figure 2. When the enabled part output is LOW, the combined line
remains LOW. If all connected AZP94 parts are disabled, both output lines will be in the LOW state. As another feature,
while disabled, the input buffer is powered down to minimize feed through.
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May 2012, Rev 2.0