HCTL-2001 Datasheet, PDF (9/12 Pages) AVAGO TECHNOLOGIES LIMITED – Quadrature Decoder/Counter Interface ICs

Quadrature Decoder
The quadrature decoder decodes the incoming filtered
signals into count information. This circuitry multiplies
the resolution of the input signals by a factor of four
(4X decoding).
The quadrature decoder samples the outputs of the
CHA and CHB filters. Based on the past binary state of
the two signals and the present state, it outputs a count
signal and a direction signal to the integral position
counter.
Figure 8 shows the quadrature states of Channel A and
Channel B signals and shows the valid state transitions
for 4x decoder. Channel A leading channel B results in
counting up. Channel B leading channel A results in
counting down. Illegal state transitions, caused by
faulty encoders or noise severe enough to pass through
the filter, will produce an erroneous count.
clk
state
1
2
3
4
chA
chB
Tes
Te
Telp
count up
1
4
Valid State
Transitions
2
3
count
down
Figure 8. 4x Decoder Mode
CHA CHB STATE
10
1
11
2
0
1
3
0
0
4
Design Considerations
The designer should be aware that the operation of
the digital filter places a timing constraint on the
relationship between incoming quadrature signals and
the external clock. Figure 7 shows the timing waveform
with an incremental encoder input. Since an input has
to be stable for three rising clock edges, the encoder
pulse width (tE - low or high) has to be greater than
three clock periods (3tCLK). This guarantees that the
asynchronous input will be stable during three
consecutive rising clock edges. A realistic design also
has to take into account finite rise time of the
waveforms, asymmetry of the waveforms, and noise.
In the presence of large amounts of noise, tE should
be much greater than 3tCLK— to allow for the
interruption of the consecutive level sampling by the
three-bit delay filter. It should be noted that a change
on the inputs that is qualified by the filter will internally
propagate in a maximum of seven clock periods.
The quadrature decoder circuitry imposes a second
timing constraint between the external clock and the
input signals. There must be at least one clock period
between consecutive quadrature states. As shown in
Figure 7, a quadrature state is defined by consecutive
edges on both channels. Therefore, tES (encoder state
period) > tCLK-. The designer must account for
deviations from the nominal 90 degree phasing of input
signals to guarantee that tES > tCLK.
Position Counter
This section consists of a 12-bit (HCTL-2001) binary up/
down counter which counts on rising clock edges as
explained in the Quadrature Decoder Section. All 12-
bit of data are passed to the position data latch. The
system can use this count data in several ways:
A. System total range is £ 12 bits, so the count represents
“absolute” position.
B. The system is cyclic with £ 12 bits of count per cycle.
RSTN (or CHI) is used to reset the counter every cycle
and the system uses the data to interpolate within
the cycle.
C. System count is > 8 or 12 bits, so the count data is
used as a relative or incremental position input for a
system software computation of absolute position.
In this case counter rollover occurs. In order to prevent
loss of position information, the processor must read
the outputs of the IC before the count increments
one-half of the maximum count capability. Two’s-
complement arithmetic is normally used to compute
position from these periodic position updates.
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