HCTL-2001 Datasheet, PDF (5/12 Pages) AVAGO TECHNOLOGIES LIMITED – Quadrature Decoder/Counter Interface ICs

Switching Characteristics
Table 5. Switching Characteristics Max/Min specifications at VDD = 5.0 ? 5%, TA = -40 to +100 OC, CL = 40 pf
Symbol Description
Min.
1
t_CLK
Clock Period
70
2
t_CHH
Pulse width, clock high
28
3
t_CD
Delay time, rising edge of clock to valid,
updated count information on D0-7
4
t_ODE
Delay time, OE fall to valid data
5
t_ODZ
6
t_SDV
Delay time, OE rise to Hi-Z state on D0-7
Delay time, SEL valid to stable, selected data byte
(delay to High Byte = delay to Low Byte)
7
t_CLH
Pulse width, clock low
28
8
t_SS
Setup time, SEL before clock fall
20
9
t_OS
Setup time, OEN before clock fall
20
10 t_SH
Hold time, SEL after clock fall
0
11 t_OH
Hold time, OE after clock fall
0
12
t_RST
Pulse width, RST low
28
13
t_DCD
Hold time, last position count stable on D0-7 after clock rise
10
14
t_DSD
Hold time, last data byte stable after next SEL state change
10
15
t_DOD
Hold time, data byte stable after OE rise
10
Max.
65
65
40
65
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5