HCTL-2001 Datasheet, PDF (10/12 Pages) AVAGO TECHNOLOGIES LIMITED – Quadrature Decoder/Counter Interface ICs

Position Data Latch
The position data latch is a 12-bit latch which captures
the position counter output data on each rising clock
edge, except when its inputs are disabled by the inhibit
logic section during two-byte read operations. The
output data is passed to the bus interface section.
When active, a signal from the inhibit logic section
prevents new data from being captured by the latch,
keeping the data stable while successive reads are
made through the bus section. The latch is
automatically re-enabled at the end of these reads. The
latch is cleared to 0 asynchronously by the RST signal.
Inhibit Logic
The Inhibit Logic Section samples the OE and SEL
signals on the falling edge of the clock and, in response
to certain conditions (see Figure 9), inhibits the position
data latch. The RST signal asynchronously clears the
inhibit logic, enabling the latch.
Bus Interface
The bus interface section consists of a 16 to 8 line
multiplexer and an 8-bit, three-state output buffer. The
multiplexer allows independent access to the low and
high bytes of the position data latch. The SEL and OE
signals determine which byte is output and whether
or not the output bus is in the high-Z state. In the
case of HCTL-2001, the data latch is 12 bit wide.
General Interfacing
The 12-bit (HCTL-2001) latch and inhibit logic allows
access to 12 bits of count with an 8-bit bus. When
only 8-bits of count are required, a simple 8-bit (1-
byte) mode is available by holding SEL high
continuously. This disables the inhibit logic. OE
provides control of the tri-state bus, and read timing is
shown in Figure 2 and 3.
For proper operation of the inhibit logic during a two-
byte read, OE and SEL must be synchronous with CLK
due to the falling edge sampling of OE and SEL.
The internal inhibit logic on the HCTL-20XX family
inhibits the transfer of data from the counter to the
position data latch during the time that the latch
outputs are being read. The inhibit logic allows the
microprocessor / microcontroller to first read the high
order 4 or 8 bits from the latch and then read the low
order 8 bits from the latch. Meanwhile, the counter
can continue to keep track of the quadrature states
from the CHA and CHB input signals.
Figure 10 shows the simplified inhibit logic circuit. The
operation of the circuitry is illustrated in the read timing
shown in Figure 11.
Step SEL
1
L
2
H
3
X
OE
CLK Inhibit Signal
Action
L
Falling
1
Set inhibit; read high byte
L
Falling
1
Read low byte; starts reset
H Falling
0
Complete inhibit logic reset
Figure 9. Two Bytes Read Sequence
Figure 10. Simplified Inhibit Logic
10