HCTL-2001 Datasheet, PDF (4/12 Pages) AVAGO TECHNOLOGIES LIMITED – Quadrature Decoder/Counter Interface ICs

Functional Pin Description
Table 4. Functional Pin Descriptions
Symbol Pin
Description
HCTL
2001
VDD 16
Power Supply
VSS
8
Ground
CLK
2
CLK is a Schmitt-trigger input for the external clock signal.
CHA 7
CHB 6
CHA and CHB are Schmitt-trigger inputs that accept the outputs from a quadrature-encoded
source, such as incremental optical shaft encoder. Two channels, A and B, nominally 90 degrees
out of phase, are required.
RST
5
OE
4
This active low Schmitt-trigger input clears the internal position counter and the position latch.
It also resets the inhibit logic. RST is asynchronous with respect to any other input signals.
This CMOS active low input enables the tri-state output buffers. The OE/ and SEL inputs are
sampled by the internal inhibit logic on the falling edge of the clock to control the loading of the
internal position data latch.
SEL
3
These CMOS inputs directly controls which data byte from the position latch is enabled into the
8-bit tri-state output buffer. As in OE/ above, SEL also control the internal inhibit logic.
SEL BYTE SELECTED
0
High
1
Low
D0
1
These LSTTL-compatible tri-state outputs form an 8-bit output ports through which the contents
D1
15
of the 16-bit position latch may be read in 2 sequential bytes. The High byte is read first
followed by the Low bytes.
D2
14
D3
13
D4
12
D5
11
D6
10
D7
9
NC
NA
Not connected - this pin should be left floating.
4