HCPL-0720-500E Datasheet, PDF (8/18 Pages) AVAGO TECHNOLOGIES LIMITED – 40 ns Propagation Delay, CMOS Optocoupler

Package Characteristics
Parameter
Symbol Min. Typ. Max. Units Test Conditions
Fig. Note
Input-Output Momentary 072X
V_ISO
3750
Vrms RH ≤50%,
8, 9,
Withstand Voltage
772X
3750
t = 1 min.,
10

Option 020
5000
T_A = 25°C
Resistance
R_I-O 10¹² Ω
V_I-O = 500 Vdc
8
(Input-Output)
Capacitance
(Input-Output)
C_I-O
0.6
pF
f = 1 MHz
Input Capacitance
C_I 3.0 11
Input IC Junction-to-Case  -772X
θ_jci 145 °C/W Thermocouple
Thermal Resistance   
-072X
160
located at center
Output IC Junction-to-Case -772X
θ_jco 140
Thermal Resistance
-072X   
135
underside of package
Package Power Dissipation
P_PD 150 mW
Notes:
  1. Absolute Maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not
guarantee functionality.
  2. The LED is ON when V_I is low and OFF when V_I is high.
  3. t_PHL propagation delay is measured from the 50% level on the falling edge of the V_I signal to the 50% level of the falling edge of the V_O signal.
t_PLH propagation delay is measured from the 50% level on the rising edge of the V_I signal to the 50% level of the rising edge of the V_O signal.
  4. PWD is defined as |t_PHL - t_PLH|. %PWD (percent pulse width distortion) is equal to the PWD divided by pulse width.
  5. t_PSK is equal to the magnitude of the worst case difference in t_PHL and/or t_PLH that will be seen between units at any given temperature within
the recommended operating conditions.
  6. CM_H is the maximum common mode voltage slew rate that can be sustained while maintaining V_O > 0.8 V_DD2. CM_L is the maximum common
mode voltage slew rate that can be sustained while maintaining V_O < 0.8 V. The common mode voltage slew rates apply to both rising and
falling common mode voltage edges.
  7. Unloaded dynamic power dissipation is calculated as follows: C_PD * V_DD2 * f + I_DD * V_DD, where f is switching frequency in MHz.
  8. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.
9. In accordance with UL1577, each HCPL-072X is proof tested by applying an insulation test voltage ≥4500 V_RMS for 1 second (leakage detection
current limit, I_I-O ≤5 µA). Each HCPL-772X is proof tested by applying an insulation test voltage ≥4500 Vrms for 1 second (leakage detection
current limit. I_I-O ≤ 5 µA.)
10. The Input-Output Momentary With­stand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to your equipment level safety specification or Avago Application Note 1074 “Optocou-
pler Input-Output Endurance Voltage.”
11. C_I is the capacitance measured at pin 2 (V_I).
5
0 °C
4
25 °C
85 °C
3
2
1
0
0
1
2
3
4
5
V_I (V)
Figure 1. Typical output voltage vs. input volt-
age
2.2
0 °C
2.1
25 °C
85 °C
2.0
1.9
1.8
1.7
1.6
4.5
4.75
5
5.25
5.5
V_DD1 (V)
Figure 2. Typical input voltage switching thresh-
old vs. input supply voltage
29
27
25
T_PLH
23
21
T_PHL
19
17
15
0 10 20 30 40 50 60 70 80
T_A (C)
Figure 3. Typical propagation delays vs. tem-
perature
8