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HCPL-0720-500E Datasheet, PDF (7/18 Pages) AVAGO TECHNOLOGIES LIMITED – 40 ns Propagation Delay, CMOS Optocoupler
Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at TA = +25 °C, VDD1 = VDD2 = +5 V.
Parameter
Symbol Min.
Typ.
Max. Units Test Conditions
Fig. Note
DC Specifications
Logic Low Input
Supply Current
IDD1L 6.0
10.0
mA
VI = 0 V
2
Logic High Input
Supply Current
IDD1H 1.5
3.0
mA
VI = VDD1
Output Supply Current
IDD2L 5.5
9.0
mA
IDD2H 7.0
9.0
Input Current
II
–10 10
µA
Logic High Output
VOH
4.4
5.0 V
IO = -20 µA, VI = VIH 1, 2
Voltage 4.0
4.8 IO = -4 mA, VI = VIH
Logic Low Output
VOL 0
0.1
V
IO = 20 µA, VI = VIL
Voltage 0.1
V
IO = 400 µA, VI = VIL
0.5
1.0 IO = 4 mA, VI = VIL
Switching Specifications
Propagation Delay Time
tPHL 20
40
ns
to Logic Low Output
CL = 15 pF
3, 6 3
CMOS Signal Levels
Propagation Delay Time
tPLH 23
40
ns
to Logic High Output
Pulse Width
PW
40 ns
Data Rate 25
MBd
Pulse Width Distortion
PWD
7721/0721 3
6
ns
7
4
|tPHL - tPLH| 7720/0720 3
8
ns
Propagation Delay Skew
tPSK 20 5
Output Rise Time
tR 9 ns
(10 - 90%)
Output Fall Time
tF 8 ns
(90 - 10%)
Common Mode
|CMH|
10
20 kV/µs
VI = VDD1, VO >
6
Transient Immunity at 0.8 VDD1,
Logic High Output VCM = 1000 V
Common Mode
|CML|
10
20 VI = 0 V, VO > 0.8 V,
Transient Immunity at VCM = 1000 V
Logic Low Output
Input Dynamic Power
Dissipation
CPD1 60 pF 7
Capacitance
Output Dynamic Power
Dissipation
CPD2 10
Capacitance
7