HCPL-0720-500E Datasheet, PDF (10/18 Pages) AVAGO TECHNOLOGIES LIMITED – 40 ns Propagation Delay, CMOS Optocoupler

Application Information
Bypassing and PC Board Layout
The HCPL-772X/072X optocouplers are extremely easy to use. No external interface circuitry is required because the
HCPL-772X/072X use high-speed CMOS IC technology allowing CMOS logic to be connected directly to the inputs
and outputs.
As shown in Figure 10, the only external components required for proper operation are two bypass capacitors. Ca-
pacitor values should be between 0.01 µF and 0.1 µF. For each capacitor, the total lead length between both ends of
the capacitor and the power-supply pins should not exceed 20 mm. Figure 11 illustrates the recommended printed
circuit board layout for the HPCL-772X/072X.
V_DD1
1
C1
V_I
2
NC 3
GND₁
4
8
C2
7 NC
V_DD2
6
V_O
5
GND₂
C1, C2 = 0.01 µF TO 0.1 µF
Figure 10. Recommended printed circuit board layout.
V_DD1
V_I
C1
GND₁
Figure 11. Recommended printed circuit board layout
V_DD2
C2
V_O
GND₂
C1, C2 = 0.01 µF TO 0.1 µF
Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew
Propagation Delay is a figure of merit that describes how quickly a logic signal propagates through a system. The
propaga­tion delay from low to high (t_PLH) is the amount of time required for an input signal to propagate to the
output, causing the output to change from low to high. Similarly, the propagation delay from high to low (t_PHL) is the
amount of time required for the input signal to propagate to the output, causing the output to change from high to
low. See Figure 12.
INPUT
V_I
OUTPUT
V_O
10%
t_PLH
90%
t_PHL
50%
90%
10%
5 V CMOS
0V
V_OH
2.5 V CMOS
V_OL
Figure 12.
10
HCPL-0710 fig 13