HCTL-2032 Datasheet, PDF (6/21 Pages) Agilent(Hewlett-Packard) – Quadrature Decoder/Counter Interface ICs

Functional Pin Description
Table 4. Functional Pin Descriptions
Symbol
V_DD
V_SS
CLK
CHA_X
CHA_Y
CHB_X
CHB_Y
CHI_X
CHI_Y
RSTN_X
RSTN_Y
OEN
SEL₁
SEL₂
Pin
HCTL
2032/ HCTL
2032-SC 2022
1
1
18
12
5
3
15
10
16
NC
14
9
13
NC
17
11
19
NC
12
8
11
NC
7
5
6
4
26
17
Description
Power Supply
Ground
CLK is a Schmitt-trigger input for the external clock signal.
CHA_X, CHA_Y, CHB_X, and CHB_Y are Schmitt-trigger inputs that accept the outputs
from a quadrature-encoded source, such as incremental optical shaft encoder. Two
channels, A and B, nominally 90 degrees out of phase, are required. CHA_X and CHB_X
are the 1st axis and CHA_Y and CHB_Y are the 2nd axis.
CHI_X and CHI_Y are Schmitt-trigger inputs that accept the outputs of Index channel
from an incremental optical shaft encoder.
This active low Schmitt-trigger input clears the internal position counter and the
position latch. It also resets the inhibit logic. RST_X/ and RST_Y/ are asynchronous with
respect to any other input signals. RST_X/ is to reset the 1st axis counter and RST_Y/ is
to reset the 2nd axis counter.
This CMOS active low input enables the tri-state output buffers. The OE/, SEL1, and
SEL2 inputs are sampled by the internal inhibit logic on the falling edge of the clock
to control the loading of the internal position data latch.
These CMOS inputs directly controls which data byte from the position latch is en-
abled into the 8-bit tri-state output buffer. As in OE/ above, SEL₁ and SEL₂ also con-
trol the internal inhibit logic.
EN₁
2
EN₂
3
X/Y
32
CNTDEC_X 27
CNTDEC_Y 28
U/Dx
8
U/Dy
9

BYTE SELECTED
SEL1
SEL2
MSB
2ND
3RD
LSB
0
1
D4
1
1
D3
0
0
D2
1
0
D1
NC These CMOS control pins are set to high or low to activate the selected count mode
NC ^{before the decoding begins.}
EN1
EN2
0
0
1
0
0
1
1
1
Count Modes
4x
2x
1x
Illegal Mode
On
On
On
NC Select the 1^st or 2^nd axis data to be read. Low bit enables the 1^st axis data, while
high bit enables the 2^nd axis data.
NC A pulse is presented on this LSTTL-compatible output when the quadrature decod-
NC ^{er (4x/2x/1x) has detected a state transition. CNTDECX is for 1st axis and CNTDECY}
is for 2^nd axis.
6
This LSTTL-compatible output allows the user to determine whether the IC is count-
NC ^{ing up or down and is intended to be used with the CNTDEC and CNTCAS outputs.}
The proper signal U (high level) or D/ (low level) will be present before the rising
edge of the CNTDEC and CNTCAS outputs.