HCTL-2032 Datasheet, PDF (21/21 Pages) Agilent(Hewlett-Packard) – Quadrature Decoder/Counter Interface ICs

Actions
1. At first, Port B4, B5, and B6 are setup for 4X encoding
and X/Y axis selection.
2. The HCTL-2032 detects that OE/ are low on the next
falling edge of the CLK and asserts the internal inhibit
signal. Data can be read without regard for the phase
of the CLK.
3. SEL1 and SEL2 are setup to select the appropriate
bytes. The “Get_hi” subroutine is called and the data is
read into the AVR.
4. Step 3 is repeated by changing the SEL1 and SEL2
combinations and specific subroutine is called to read
in the appropriate data.
5. The HCTL-2032 detects OE/ high on the next falling
edge of the CLK. The program set OE/ high by writing
the correct value to the respective Port. This causes
the data lines to be tristated. On the next rising CLK
edge new data is transferred from the counter to the
position data latch.
6. For displaying purposes, the data is arranged in 32-
bit data by shifting the MSB to the left through
multiplication.
Ordering Information
HCTL - 20 XX - XX
32 Blank
32 SC
32 SCT
22 Blank
32-PDIP Package
32-SOIC Package
32-SOIC Package in Tape and Reel (1000 Pcs / Reel)
20-PDIP Package
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Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes 5989-0060EN
AV02-0096EN - January 16, 2007
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