HCTL-2032 Datasheet, PDF (15/21 Pages) Agilent(Hewlett-Packard) – Quadrature Decoder/Counter Interface ICs

CHA
CHB
STATE
1
0
1
1
1
2
0
1
3
0
0
4
Figure 13. 4x Decoder Mode
4X Decoder
(Count Up & Count Down)
Pulse
Pulse
Pulse
Pulse
CHA
CHB
STATE
1
0
1
1
1
2
0
1
3
0
0
4
Figure 14. 2x and 1x Decoder Modes
2x
Count Up
Pulse
-
Pulse
-
2x
Count Down
-
Pulse
-
Pulse
1x
Count Up
Pulse
-
-
-
1x
Count Down
-
Pulse
-
-
Design Considerations
The designer should be aware that the operation of the
digital filter places a timing constraint on the relationship
between incoming quadrature signals and the external
clock. Figure 12 shows the timing waveform with an in-
cremental encoder input. Since an input has to be stable
for three rising clock edges, the encoder pulse width (t_E
- low or high) has to be greater than three clock periods
(3t_CLK). This guarantees that the asynchronous input will
be stable during three consecutive rising clock edges. A
realistic design also has to take into account finite rise
time of the waveforms, asymmetry of the waveforms,
and noise. In the presence of large amounts of noise, t_E
should be much greater than 3t_CLK to allow for the inter-
ruption of the consecutive level sampling by the three-
bit delay filter. It should be noted that a change on the
inputs that is qualified by the filter will internally propa-
gate in a maximum of seven clock periods.
The quadrature decoder circuitry imposes a second tim-
ing constraint between the external clock and the input
signals. There must be at least one clock period between
consecutive quadrature states. As shown in Figure 13,
a quadrature state is defined by consecutive edges on
both channels. Therefore, t_ES (encoder state period) >
t_CLK. The designer must account for deviations from the
nominal 90 degree phasing of input signals to guarantee
that t_ES > t_CLK.
Position Counter
This section consists of a 32-bit (HCTL-20XX-XX) binary
up/down counter which counts on rising clock edges as
explained in the Quadrature Decoder Section. All 32 bits
of data are passed to the position data latch. The system
can use this count data in several ways:
A. System total range is 32 bits, so the count represents
“absolute” position.
B. The system is cyclic with 32 bits of count per cycle.
RST/ is used to reset the counter every cycle and the
system uses the data to interpolate within the cycle.
C. System count is >8, 16, 24, or 32 bits, so the count data
is used as a relative or incremental position input for a
system software computation of absolute position. In
this case counter rollover occurs. In order to prevent
loss of position information, the processor must read
the outputs of the IC before the count increments
one-half of the maximum count capability. Two’s-
complement arithmetic is normally used to compute
position from these periodic position updates.
D. The system count is >32 bits so the HCTL-2032 / 2032-
SC can be cascaded with other standard counter ICs to
give absolute position.
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