HCTL-2032 Datasheet, PDF (16/21 Pages) Agilent(Hewlett-Packard) – Quadrature Decoder/Counter Interface ICs

Position Data Latch
Quadrature Decoder Output (HCTL-2032 / 2032-SC only)
The position data latch is a 32-bit latch which captures
the position counter output data on each rising clock
edge, except when its inputs are disabled by the inhibit
logic section during four-byte read operations. The out-
put data is passed to the bus interface section. When ac-
tive, a signal from the inhibit logic section prevents new
data from being captured by the latch, keeping the data
stable while successive reads are made through the bus
section. The latch is automatically re-enabled at the end
of these reads. The latch is cleared to 0 asynchronously by
the RST signal.
The quadrature decoder output section consists of count
and up/down outputs derived from the 4x/2x/1x decod-
er mode of the HCTL-2032 / 2032-SC. When the decoder
has detected a count, a pulse, one-half clock cycle long,
will be output on the CNT_DCDR pin. This output will oc-
cur during the clock cycle in which the internal counter
is updated. The U/D pin will be set to the proper voltage
level one clock cycle before the rising edge of the CNT-
DCDR ^{pulse, and held one clock cycle after the rising edge}
of the CNT_DCDR pulse. These outputs are not affected by
the inhibit logic.
Inhibit Logic
Cascade Output (HCTL-2032 / 2032-SC only)
The Inhibit Logic Section samples the OE, SEL1 and SEL2
signals on the falling edge of the clock and, in response
to certain conditions (see Figure 15), inhibits the position
data latch. The RST signal asynchronously clears the in-
hibit logic, enabling the latch.
Bus Interface
The bus interface section consists of a 32 to 8 line multi-
plexer and an 8-bit, three-state output buffer. The mul-
tiplexer allows independent access to the low and high
bytes of the position data latch. The SEL1, SEL2 and OE
signals determine which byte is output and whether or
not the output bus is in the high-Z state. In the HCTL-
20XX-XX, the data latch is 32 bit wide.
The cascade output also consists of count and up/down
outputs. When the HCTL-2032 / 2032-SC internal coun-
ter overflows or underflows, a pulse, one-half clock cycle
long, will be output on the CNT_CAS pin. This output will
occur during the clock cycle in which the internal coun-
ter is updated. The U/D pin will be set to the proper volt-
age level one clock cycle before the rising edge of the
CNT_CAS pulse, and held one clock cycle after the rising
edge of the CNT_CAS pulse. These outputs are not affected
by the inhibit logic.
Step
SEL1
SEL2
OE
CLK
1
L
H
L
2
H
H
L
3
L
L
L
4
H
L
L
5
X
X
H
Figure 15. Four Bytes Read Sequence
Inhibit Signal
1
1
1
1
0
Action
Set inhibit; Read MSB
Read ^2nd Byte
Read 3^rd Byte
Read LSB
Completes inhibit logic reset
16