HCTL-2032 Datasheet, PDF (12/21 Pages) Agilent(Hewlett-Packard) – Quadrature Decoder/Counter Interface ICs

Operation
A block diagram of the HCTL-20XX-XX family is shown
in Figure 10. The operation of each major function is de-
scribed in the following sections.
CLK
CHAX
CHBX
CHAY
CHBY
CHIX
CHIY
Digital Filter
CHAX filtered
CHBX filtered
CHAY filtered
CHBY filtered
CHIX filtered
CHIY filtered
4x/2x/1x
Decode Logic
CNTX
UP/DN X
CNTY
UP/DN Y
EN1 EN2
32 Bits Binary
Counter
QX0 - QX31
QY0 - QY31
CNTX
UP/DN X
CNTY
UP/DN Y
CLRX
CLRY
RX RY
Decode / Cascade
Outputs (Y)
U/DY
CNTDECY
CNTCASY
Decode / Cascade
Outputs (X)
U/DX
CNTDECX
CNTCASX
32 Bits Latch
DX0 - DX31
32
DY0 - DY31
32
8
DX0 - DX7
DX8 - DX15 ⁸
DX16 - DX23 ⁸
DX24 - DX31 ⁸
DY0 - DY7
8
DY8 - DY15 ⁸
DY16 - DY23 ⁸
DY24 - DY31 ⁸
CLRX
CLRY
INHX INHY
Octal 4 bit
Mux/Buffer
D0 - D7 ⁸
DX0 - DX7
DX8 - DX15
DX16 - DX23
DX24 - DX31
DY0 - DY7
DY8 - DY15
DY16 - DY23
DY24 - DY31
SEL1
SEL2
OE XNY
RSTX
RSTY
EN1
EN2
SEL1
SEL2
OE
XNY
Figure 10. Simplified Logic Diagram
Inhibit Block
CLRX
CLRY
SEL1 SEL2 OE
12