HCMS-2819 Datasheet, PDF (6/12 Pages) AVAGO TECHNOLOGIES LIMITED – High Performance CMOS 5x7 AlphaNumeric InGaN Blue Display

Dot Register
The Dot Register holds the pattern to be displayed by the
LEDs. Data is loaded into the Dot Register according to the
procedure shown in Table 1 and Figure 2.
First RS is brought low, then CE is brought low. Next, each
successive rising CLK edge will shift in the data at the
DIN pin. Loading a logic high will turn the corresponding
LED on; a logic low turns the LED off. When all 160 bits
have been loaded (or 320 bits in an 8-digit display), CE is
brought to logic high.
When CLK is next brought to logic low, new data is
latched into the display dot drivers. Loading data into
the Dot Register takes place while the previous data is
displayed and eliminates the need to blank the display
while loading data.
Table 1. Register Truth Table
Function
Select Dot Register
Load Dot Register
DIN = HIGH, LED = “ON”
DIN = LOW, LED = “OFF”
Copy Data from Dot
Register to Dot Latch
Select Control Register
Load Control Register ^[1,3]
Latch Data to Control Word ^[2]
CLK
Not
Rising
Rising
L
Not
Rising
Rising
L
CE
RS
Falling
L
X
H
X
Falling H
L
X
H
X
Notes:
1. Bit D₀ of Control Word 1 must have been preciously set to Low for
serial mode or High for simultaneous mode.
2. Selection of Control Word 1 or Control Word 0 is set by D₇ of the
Control Shift Register. The unselected control word retains its previ-
ous value.
3. Control Word data is loaded Most Significant Bit (D₇) first.
RS
CE
CLK
D _IN
D OUT(SERIAL)
D _OUT
(SIMULTANEOUS)
T_RSS
1
T_RSH
2
T _CLKCE
3
T _CES
4
T _CLKH
11
T _CEDO
10
T_{DS T DH}
6
7
T_DOUT
8
T _DOUTP
9
T_CLKL
12
T _CEH
5
[1]
NEW DATA LATCHED HERE
LED OUTPUTS,
CONTROL
REGISTERS
PREVIOUS DATA
NOTE:
1. DATA IS COPIED TO THE CONTROL REGISTER OR THE DOT LATCH AND LED OUTPUTS WHEN CE IS HIGH AND CLK IS LOW.
Figure 2. Write Cycle Timing Diagram
NEW DATA
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