HBCU-5710R Datasheet, PDF (2/25 Pages) AVAGO TECHNOLOGIES LIMITED – Designed for Industry-Standard MSA-Compliant, Small Form Factor Pluggable (SFP) Ports

Module Diagrams
Figure 1 illustrates the major functional components
of the HBCU-5710R. The 20-pin connection diagram of
module printed circuit board of the module is shown in
Figure 2. Figure 3 depicts the pin assignment of the MDI
(RJ45 jack).
Figure 7 depicts the external configuration and dimen-
sions of the module.
Installation
The HBCU-5710R can be installed in or removed from
any MultiSource Agreement (MSA) compliant Small Form
Pluggable port whether the host equipment is operating
or not. The module is simply inserted, small end first, un-
der finger-pressure. Controlled hot-plugging is ensured
by design and by 3-stage pin sequencing at the electrical
interface to the host board. The module housing makes
initial contact with the host board EMI shield, mitigating
potential damage due to Electro-Static Discharge (ESD).
The module pins sequentially contact the (1) Ground,
(2) Power, and (3) Signal pins of the host board surface
mount connector. This printed circuit board card-edge
connector is depicted in Figure 2.
Serial Identification (EEPROM)
The HBCU-5710R complies with an industry standard
MultiSource Agreement that defines the serial identifica-
tion protocol. This protocol uses the 2-wire serial CMOS
EEPROM protocol of the ATMEL AT24C01A or equivalent.
The contents of the HBCU-5710R serial ID memory are
defined in Table 3 as specified in the SFP MSA.
Controller and Data I/O
Data I/Os are designed to accept industry standard dif-
ferential signals. In order to reduce the number of passive
components required on the customer’s board, Avago
Technologies has included the functionality of the trans-
mitter bias resistors and coupling capacitors within the
module. The transceiver is compatible with an “ac-cou-
pled” configuration and is internally terminated. Figure
1 depicts the functional diagram of the HBCU-5710R.
Caution should be taken into account for the proper
interconnection between the supporting Physical Layer
integrated circuits and the HBCU-5710R. Figure 4 illus-
trates the recommended interface circuit.
Several control data signals and timing diagrams are imple-
mented in the module and are depicted in Figure 6.
20
V_EET
19
TD-
18
TD+
17
V_EET
16
V_CCT
15
V_CCR
14
V_EER
13
RD+
12
RD-
11
V_EER
1
V_EET
2
TX_FAULT
3
TX_DISABLE
4
MOD-DEF(2)
5
MOD-DEF(1)
6
MOD-DEF(0)
7
Rate Select
8
LOS
9
V_EER
10
V_EER
Top of Board
Bottom of Board
(as viewed thru top of board)
Note: TX_FAULT and Rate_Select not used.
Figure 2: 20-pin Connection Diagram of Module Printed Circuit Board
TX_DATA
RX_DATA
TX_DISABLE
TX_FAULT
RX_LOS
RATE_SELECT NC
MOD_DEF2
MOD_DEF1
MOD_DEF0
SerDes/
DSP
A
B
C
Magnetics
RJ45
Adapter
D
EEPROM
Figure 1: Transceiver Functional Diagram