HBCU-5710R Datasheet, PDF (12/25 Pages) AVAGO TECHNOLOGIES LIMITED – Designed for Industry-Standard MSA-Compliant, Small Form Factor Pluggable (SFP) Ports

Table 5: Register 0 (Control)
Bit
Name
0.15
Reset
R/W
0.14
Loopback
R/W
Description
1 = PHY reset
0 = Normal Operation
1 = Enable
0 = Disable
0.13
Speed Selection (LSB) 0 = 1000 Mb/s
R/W
Hardware
Reset
0
0
Software
Reset
self-
clearing
0
0
Update
0.12
R/W
0.11
R/W
0.10
R/W
0.9
R/W/SC
0.8
R/W
0.7
R/W
0.6
R/W
Auto-Negotiation
1 = Enable
0
Enable
0 = Disable
Power Down
1 = Power Down
0
0 = Normal Operation
Isolate
1 = Isolate
0
0 = Normal Operation
Restart
Auto-Negotiation
1 = Restart Auto-Negotiation Process 0
0 = normal operation
Duplex Mode
1 = Full Duplex
1
0 = Half Duplex
Collision Test
1 = enable COL signal test
0
0 = disable COL signal test
Speed Selection (MSB) 1 = 1000 Mb/s
1
Update
0
0
Self-
clearing
Update
0
Update
0.5:0
N/A to SFP Module
R/W
000000
000000
Details
Performs software reset
Serial data in on RD+/- is deserial-
ized, then reserialized and sent out
on TD+/-
Paired with bit 0.6. Other settings
indicate different speeds, but the
module will not function at speeds
other than 1000 Mb/s. This bit is
only meaningful if bit 0.12 is 0.
Changes to this bit take effect after
software reset.
This bit is only meaningful if 0.12
is 0.
Paired with bit 0.13. Other settings
indicate different speeds, but the
module will not function at speeds
other than 1000 Mb/s. This bit is
only meaningful if bit 0.12 is 0.
12