HBCU-5710R Datasheet, PDF (16/25 Pages) AVAGO TECHNOLOGIES LIMITED – Designed for Industry-Standard MSA-Compliant, Small Form Factor Pluggable (SFP) Ports

Table 12: Register 9 (MASTER-SLAVE Control)
Bit
9.15:13
R/W
Name
Transmitter Test
Mode
9.12 MASTER-SLAVE
R/W Manual Config
Enable
9.11 MASTER-SLAVE
R/W Config Value
9.10 Port Type
R/W
Description
Hardware
Reset
000 = Normal Operation
000
001 = Transmit Waveform Test
010 = Transmit Jitter Test in MASTER Mode
011 = Transmit Jitter Test in SLAVE Mode
1 = Enable MASTER-SLAVE Manual configuration 0
value in register 9.11
0 = Disable MASTER-SLAVE Manual configuration
value in register 9.11
1 = Configure PHY as MASTER during MASTER-SLAVE 1
negotiation
0 = Configure PHY as SLAVE during MASTER-SLAVE
negotiation
1 = Prefer PHY as MASTER (multiport)
1
0 = Prefer PHY as SLAVE (single port)
9.9
1000BASE-T
R/W Full Duplex
9.8
1000BASE-T
R/W Half Duplex
9.7:0 N/A to SFP
RO
Module
1 = Advertise PHY is 1000BASE-T full duplex capable 1
0 = Advertise PHY is not 1000BASE-T full duplex
capable
1 = Advertise PHY is 1000BASE-T half duplex capable 0
0 = Advertise PHY is not 1000BASE-T half duplex
capable
00000000
Software
Reset
000
Retain
Retain
Retain
Retain
Retain
00000000
Details
The module enters test modes
when MDI crossover is first
disabled via bits 16.6:5.
This bit takes effect after auto-
negotiation is restarted via bit
0.9.
This bit takes effect after auto-
negotiation is restarted via bit
0.9. This bit is ignored unless bit
9.12 is 1.
This bit takes effect after auto-
negotiation is restarted via bit
0.9. This bit is ignored unless bit
9.12 is 0.
This bit takes effect after auto-
negotiation is restarted via bit
0.9.
This bit takes effect after auto-
negotiation is restarted via bit
0.9.
16