HBCU-5710R Datasheet, PDF (11/25 Pages) AVAGO TECHNOLOGIES LIMITED – Designed for Industry-Standard MSA-Compliant, Small Form Factor Pluggable (SFP) Ports

Internal ASIC Registers
The ASIC (or “PHY”, for Physical Layer IC) in the transceiver
module contains 32 registers. Each register contains 16
bits. The registers are summarized in Table 4 and detailed
in Tables 5 through 22. Each bit is either Read Only (RO) or
Read/Write (R/W). Some bits are also described as Latch
High (LH) or Latch Low (LL) and/or Self Clearing (SC).
The registers are accessible through the 2-wire se-
rial CMOS EEPROM protocol of the ATMEL AT24C01A or
equivalent. The address of the PHY is 1010110x, where x
is the R/W bit. Each register’s address is 000yyyyy, where
yyyyy is the binary equivalent of the register number.
Write and read operations must send or receive 16 bits of
data, so the “multi-page” access protocol must be used.
Table 4. Summary of Internal IC Registers at address AC
Register
0
1
2-3
4
5
6
7
8
9
10
11-15
16
17
18-19
20
21
22
23
26
27
28
29-30
31
Description
Control
Status
N/A for SFP Module
Auto-Negotiation Advertisement
Auto-Negotiation Link Partner Ability
Auto-Negotiation Expansion
Auto-Negotiation Next Page Transmit
Auto-Negotiation Link Partner Received Next Page
MASTER-SLAVE Control Register
MASTER-SLAVE Status Register
N/A for SFP Module
Extended Control 1
Extended Status 1
N/A for SFP Module
Extended Control 2
Receive Error Counter
Cable Diagnostic 1
N/A for SFP Module
Extended Control 3
Extended Status 2
Cable Diagnostic 2
Specific Function Registers
N/A for SFP Module
11