HCPL-3180-500E Datasheet, PDF (15/16 Pages) AVAGO TECHNOLOGIES LIMITED – 2.5 Amp Output Current, High Speed, Gate Drive Optocoupler

1
8
+5 V
C_LEDP
2
7
3
6
Q1
C_LEDN
I_LEDN
4
5
SHIELD
Figure 31. Not recommended open collector drive circuit.
1
8
+5 V
C_LEDP
2
7
3
6
C_LEDN
4
5
SHIELD
Figure 32. Recommended LED drive circuit for ultra-high CMR.
Under Voltage Lockout Feature
The HCPL-3180 contains an under voltage lockout (UVLO)
feature that is designed to protect the IGBT under fault
conditions which cause the HCPL-3180 supply voltage
(equivalent to the fully charged IGBT gate voltage) to
drop below a level necessary to keep the IGBT in a low
resistance state. When the HCPL-3180 output is in the
high state and the supply voltage drops below the HCPL-
3180 V_UVLO- threshold (typ 7.5 V) the optocoupler output
will go into the low state. When the HCPL-3180 output is
in the low state and the supply voltage rises above the
HCPL-3180 V_UVLO+ threshold (typ 8.5 V) the optocoupler
output will go into the high state (assume LED is “ON”).
IPM Dead Time and Propagation Delay Specifications
The HCPL-3180 includes a Propagation Delay Difference
(PDD) specification intended to help designers minimize
“dead time” in their power inverter designs. Dead time is
the time during which the high and low side power tran-
sistors are off. Any overlap in Q1 and Q2 conduction will
result in large currents flowing through the power devices
from the high voltage to the low-voltage motor rails.
To minimize dead time in a given design, the turn on of
LED2 should be delayed (relative to the turn off of LED1)
so that under worst-case conditions, transistor Q1 has
just turned off when transistor Q2 turns on, as shown in
Figure 34. The amount of delay necessary to achieve this
condition is equal to the maximum value of the propa-
gation delay difference specification, PDD_MAX, which is
specified to be 90 ns over the operating temperature
range of -40 °C to +100 °C.
20
18
16
14
12
10
8
6
4
2
0
0
5
10
15
20
(V_CC - V_EE) – SUPPLY VOLTAGE – V
Figure 33. Under voltage lock out.
I_LED1
V_OUT1
V_OUT2
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
I_LED2
t_{PHL MAX}
t_{PLH MIN}
PDD* MAX = (t_PHL- t_PLH)_MAX = t_{PHL MAX} - t_{PLH MIN}
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR PDD CALCULATIONS, THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
Figure 34. Minimum LED skew for zero dead time.