HCPL-3180-500E Datasheet, PDF (11/16 Pages) AVAGO TECHNOLOGIES LIMITED – 2.5 Amp Output Current, High Speed, Gate Drive Optocoupler

1
8
I_F = 10 to 16 mA
2
7
+ ^{500 Ω}
250 KHz ^–
50% DUTY
3
6
CYCLE
4
5
Figure 23. t_PLH, t_PHL, t_r and t_f test circuit and waveform.
0.1 µF
+
–
V_CC = 20 V
V_O
10 Ω
10 nF
I_F
t_r
V_OUT
t_PLH
t_f
90%
50%
10%
t_PHL
V_CM
1
I_F
A
5V
+
–
B
2
3
8
0.1 µF
7
0V
V_O
+
–
V_CC = 20 V
∆t
6
V_O
4
5
SWITCH AT A: I_F = 10 mA
V_O
+
V_CM = 1500 V
SWITCH AT B: I_F = 0 mA
Figure 24. CMR test circuit and waveform.
δV ₌ V_CM
δt ∆t
V_OH
V_OL
Applications Information Eliminating Negative IGBT Gate
Drive
To keep the IGBT firmly off, the HCPL-3180 has a very
low maximum V_OL specification of 0.4 V. The HCPL-3180
realizes the very low V_OL by using a DMOS transistor with
1 W (typical) on resistance in its pull down circuit. When
the HCPL-3180 is in the low state, the IGBT gate is shorted
to the emitter by R_g + 1 W. Minimizing R_g and the lead
inductance from the HCPL-3180 to the IGBT gate and
emitter (possibly by mounting HCPL-3180 on a small PC
board directly above the IGBT) can eliminate the need for
negative IGBT gate drive in many applications as shown
in Figure 25. Care should be taken with such a PC board
design to avoid routing the IGBT collector or emitter
traces close to the HCPL-3180 input as this can result in
unwanted coupling of transient signals into the input of
HCPL-3180 and degrade performance.
(If the IGBT drain must be routed near the HCPL-3180
input, then the LED should be reverse biased when in the
off state to prevent the transient signals coupled from the
IGBT drain from turning on the HCPL-3180.)
+5 V
1
270 Ω
2
CONTROL
INPUT
3
74XXX
OPEN
4
COLLECTOR
8
0.1 µF
7
6
5
Figure 25. Recommended LED drive and application circuit for HCPL-3180.
+ ^{VCC = 15 V}
–
Rg
Q1
Q2
11
+ HVDC
3-PHASE
AC
- HVDC