AT572D940HF_14 Datasheet, PDF (95/745 Pages) ATMEL Corporation – High Performance MagicV VLIW DSP

AT572D940HF Preliminary
As soon as a software operation is detected, the bit SRCMP (Software Reset Command in
Progress) is set in the Status Register (RSTC_SR). It is cleared as soon as the software reset is
left. No other software reset can be performed while the SRCMP bit is set, and writing any value
in RSTC_CR has no effect.
Figure 10-5. Software Reset
SLCK
MCK
Write RSTC_CR
proc_nreset
if PROCRST=1
RSTTYP
periph_nreset
if PERRST=1
NRST
(nrst_out)
if EXTRST=1
SRCMP in RSTC_SR
Any
Freq.
Resynch.
1 cycle
Processor Startup
= 3 cycles
Any
XXX
0x3 = Software Reset
EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
10.3.3.4
Watchdog Reset
The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 2 Slow Clock
cycles.
When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in
WDT_MR:
• If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST
line is also asserted, depending on the programming of the field ERSTL. However, the
resulting low level on NRST does not result in a User Reset state.
• If WDRPROC = 1, only the processor reset is asserted.
The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a
processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog
Reset, and the Watchdog is enabled by default and with a period set to a maximum.
When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset
controller.
95
7010A–DSP–07/08