AT572D940HF_14 Datasheet, PDF (201/745 Pages) ATMEL Corporation – High Performance MagicV VLIW DSP

AT572D940HF Preliminary
Figure 17-3. Read Burst, 32-bit SDRAM Access
SDCS
t_RCD = 3
CAS = 2
SDCK
SDRAMC_A[12:0]
Row n
col a
col b col c col d col e col f
RAS
CAS
SDWE
D[31:0]
(Input)
Dna Dnb Dnc Dnd Dne Dnf
17.5.3
Border Management
When the memory row boundary has been reached, an automatic page break is inserted. In this
case, the SDRAM controller generates a precharge command, activates the new row and ini-
tiates a read or write command. To comply with SDRAM timing parameters, an additional clock
cycle is inserted between the precharge/active (t_RP) command and the active/read (t_RCD) com-
mand. This is described in Figure 17-4 below.
7010A–DSP–07/08
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