AT572D940HF_14 Datasheet, PDF (90/745 Pages) ATMEL Corporation – High Performance MagicV VLIW DSP

• The code is always downloaded from the device address 0x0000_0000 to the address
0x0000_0000 of the internal SRAM (after remap).
• The downloaded code must be position-independent or linked at address 0x0000_0000.
• The DataFlash must be connected to NPCS0 of the SPI.
The SPI and MCI drivers use several PIOs in alternate functions to communicate with the
devices. Care must be taken when these PIOs are used by the application. The devices con-
nected could be unintentionally driven at boot time, and electrical conflicts between SPI output
pins and the connected devices may occur.
It is recommended to plug in critical devices to other pins to ensure correct functionality.
Table 9-5 contains a list of pins that are driven during the boot program execution. These pins
are driven during the boot sequence for a period of less than 1 second if no correct boot program
is found.
For the DataFlash driven by the SPCK signal at 8 MHz, the time to download 40 K bytes is
reduced to 68 ms.
For the SD Card driven by the MCCK signal at 12 MHz the time to download 40 K bytes is
reduced to 6.8 ms.
Before performing the jump to the application in the internal SRAM, all the PIOs and peripherals
used in the boot program are set to their reset state.
Table 9-5.
Peripheral
SPI0
SPI0
SPI0
SPI0
DBGU
DBGU
MCI
MCI
MCI
MCI
MCI
MCI
Pins Driven during Boot Program Execution
Pin
MOSI
MISO
SPCK
NPCS0
DRXD
DTXD
MCCK
MCCDA
MCDA0
MCDA1
MCDA2
MCDA3
PIO Line
PIOA1
PIOA0
PIOA2
PIOA3
PIOA9
PIOA10
PIOC22
PIOC23
PIOC24
PIOC25
PIOC26
PIOC27
10. Reset Controller (RSTC)
10.1 Description
The Reset Controller (RSTC), based on power-on reset cells, handles all the system resets with-
out any external component. It reports which reset occurred last.
The Reset Controller also drives independently or simultaneously the external reset and the
peripheral and processor resets.
90 AT572D940HF Preliminary
7010A–DSP–07/08