AT91SAM7A3_14 Datasheet, PDF (94/594 Pages) ATMEL Corporation – High-performance 32-bit RISC Architecture

19.4 Memory Controller (MC) User Interface
Base Address: 0xFFFFFF00
Table 19-1.
Offset
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
0x40
0x44
0x48
0x4C
0x50
0x54
0x60
Memory Controller (MC) Memory Mapping
Register
MC Remap Control Register
MC Abort Status Register
MC Abort Address Status Register
Reserved
MC Protection Unit Area 0
MC Protection Unit Area 1
MC Protection Unit Area 2
MC Protection Unit Area 3
MC Protection Unit Area 4
MC Protection Unit Area 5
MC Protection Unit Area 6
MC Protection Unit Area 7
MC Protection Unit Area 8
MC Protection Unit Area 9
MC Protection Unit Area 10
MC Protection Unit Area 11
MC Protection Unit Area 12
MC Protection Unit Area 13
MC Protection Unit Area 14
MC Protection Unit Area 15
MC Protection Unit Peripherals
MC Protection Unit Enable Register
EFC Configuration Registers
Name
MC_RCR
MC_ASR
MC_AASR
MC_PUIA0
MC_PUIA1
MC_PUIA2
MC_PUIA3
MC_PUIA4
MC_PUIA5
MC_PUIA6
MC_PUIA7
MC_PUIA8
MC_PUIA9
MC_PUIA10
MC_PUIA11
MC_PUIA12
MC_PUIA13
MC_PUIA14
MC_PUIA15
MC_PUP
MC_PUER
Access
Write-only
Read-only
Read-only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
See EFC Part
Reset State
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
94 AT91SAM7A3 Preliminary
6042E–ATARM–14-Dec-06