AT91SAM7A3_14 Datasheet, PDF (102/594 Pages) ATMEL Corporation – High-performance 32-bit RISC Architecture

Figure 20-1. Embedded Flash Memory Mapping
Start Address
Flash Memory
Locked Region Area
Lock Region 0
Lock Region 1
Page 0
Lock Bit 0
Lock Bit 1
Page (m-1)
Unlockable Area
Start Address + Flash Size -1
32 bits wide
Lock Region (n-1)
Lock Bit n-1 ^{Page ( (n-1)*m )}
Page (n*m-1)
20.2.2
Read Operations
An optimized controller manages embedded Flash reads. A system of 2 x 32-bit buffers is
added in order to start access at following address during the second read, thus increasing
performance when the processor is running in Thumb mode (16-bit instruction set). See Fig-
ure 20-2, Figure 20-3 and Figure 20-4.
This optimization concerns only Code Fetch and not Data.
The read operations can be performed with or without wait state. Up to 3 wait states can be
programmed in the field FWS (Flash Wait State) in the Flash Mode Register MC_FMR (see
”MC Flash Mode Register” on page 110). Defining FWS to be 0 enables the single-cycle
access of the embedded Flash.
The Flash memory is accessible through 8-, 16- and 32-bit reads.
As the Flash block size is smaller than the address space reserved for the internal memory
area, the embedded Flash wraps around the address space and appears to be repeated
within it.
102 AT91SAM7A3 Preliminary
6042E–ATARM–14-Dec-06