AT91SAM7A3_14 Datasheet, PDF (279/594 Pages) ATMEL Corporation – High-performance 32-bit RISC Architecture

AT91SAM7A3 Preliminary
Table 29-2. Baud Rate Example (OVER = 0) (Continued)
Expected Baud
Source Clock
Rate
Calculation Result
CD
14 318 180
38 400
23.30
23
14 745 600
38 400
24.00
24
18 432 000
38 400
30.00
30
24 000 000
38 400
39.06
39
24 576 000
38 400
40.00
40
25 000 000
38 400
40.69
40
32 000 000
38 400
52.08
52
32 768 000
38 400
53.33
53
33 000 000
38 400
53.71
54
40 000 000
38 400
65.10
65
50 000 000
38 400
81.38
81
Actual Baud Rate
38 908.10
38 400.00
38 400.00
38 461.54
38 400.00
38 109.76
38 461.54
38 641.51
38 194.44
38 461.54
38 580.25
Error
1.31%
0.00%
0.00%
0.16%
0.00%
0.76%
0.16%
0.63%
0.54%
0.16%
0.47%
The baud rate is calculated with the following formula:
BaudRate = MCK ⁄ CD × 16
The baud rate error is calculated with the following formula. It is not recommended to work
with an error higher than 5%.
Error
=
1
–
⎛
⎝
E_----A-x_---pc_---et_--u-c_--a-t_--e_-l--Bd---B_{-a---ua----du---Rd---}R_-a---ta--e--t_--e_{-⎠⎞}
29.5.1.3
Baud Rate in Synchronous Mode
If the USART is programmed to operate in synchronous mode, the selected clock is simply
divided by the field CD in US_BRGR.
BaudRate = ^S----^e---^l--^e---^c---^t--^e---^d---^C-----^l--^o---^c---^k-
CD
In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided
directly by the signal on the USART SCK pin. No division is active. The value written in
US_BRGR has no effect. The external clock frequency must be at least 4.5 times lower than
the system clock.
When either the external clock SCK or the internal clock divided (MCK/DIV) is selected, the
value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on
the SCK pin. If the internal clock MCK is selected, the Baud Rate Generator ensures a 50:50
duty cycle on the SCK pin, even if the value programmed in CD is odd.
6042E–ATARM–14-Dec-06
279