SAM9G35_14 Datasheet, PDF (831/1293 Pages) ATMEL Corporation – ARM-based Embedded MPU

Figure 39-29.Connection of a Smart Card to the USART
USART
SCK
TXD
CLK
Smart
Card
I/O
When operating in ISO7816, either in T = 0 or T = 1 modes, the character format is fixed. The configuration is 8 data bits,
even parity and 1 or 2 stop bits, regardless of the values programmed in the CHRL, MODE9, PAR and CHMODE fields.
MSBF can be used to transmit LSB or MSB first. Parity Bit (PAR) can be used to transmit in normal or inverse mode.
Refer to “USART Mode Register” on page 861 and “PAR: Parity Type” on page 862.
The USART cannot operate concurrently in both receiver and transmitter modes as the communication is unidirectional
at a time. It has to be configured according to the required mode by enabling or disabling either the receiver or the
transmitter as desired. Enabling both the receiver and the transmitter at the same time in ISO7816 mode may lead to
unpredictable results.
The ISO7816 specification defines an inverse transmission format. Data bits of the character must be transmitted on the
I/O line at their negative value.
39.7.4.2 Protocol T = 0
In T = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts
two bit times. The transmitter shifts out the bits and does not drive the I/O line during the guard time.
If no parity error is detected, the I/O line remains to 1 during the guard time and the transmitter can continue with the
transmission of the next character, as shown in Figure 39-30.
If a parity error is detected by the receiver, it drives the I/O line to 0 during the guard time, as shown in Figure 39-31. This
error bit is also named NACK, for Non Acknowledge. In this case, the character lasts 1 bit time more, as the guard time
length is the same and is added to the error bit time which lasts 1 bit time.
When the USART is the receiver and it detects an error, it does not load the erroneous character in the Receive Holding
Register (US_RHR). It appropriately sets the PARE bit in the Status Register (US_SR) so that the software can handle
the error.
Figure 39-30.T = 0 Protocol without Parity Error
Baud Rate
Clock
RXD
Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Guard Next
Bit
Bit Time 1 Time 2 Start
Bit
Figure 39-31.T = 0 Protocol with Parity Error
Baud Rate
Clock
I/O
Error
Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard
Bit
Bit Time 1
Guard Start D0 D1
Time 2 Bit
Repetition
SAM9G35 [DATASHEET]
11053E–ATARM–10-Mar-2014
831