SAM9G35_14 Datasheet, PDF (458/1293 Pages) ATMEL Corporation – ARM-based Embedded MPU

30.7.2 DDRSDRC Refresh Timer Register
Name:
DDRSDRC_RTR
Address: 0xFFFFE804
Access:
Read-write
Reset:
See Table 30-16
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
COUNT
7
6
5
4
3
2
1
0
COUNT
This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 472.
• COUNT: DDRSDRC Refresh Timer Count
This 12-bit field is loaded into a timer which generates the refresh pulse. Each time the refresh pulse is generated, a refresh
sequence is initiated.
SDRAM devices require a refresh of all rows every 64 ms. The value to be loaded depends on the DDRSDRC clock frequency
(MCK: Master Clock) and the number of rows in the device.
For example, for an SDRAM with 8192 rows and a 100 MHz Master clock, the value of Refresh Timer Count bit is programmed:
(((64 x 10^-3)/8192) x100 x10⁶ )= 781 or 0x030D.
SAM9G35 [DATASHEET]
11053E–ATARM–10-Mar-2014
458