SAM9G35_14 Datasheet, PDF (176/1293 Pages) ATMEL Corporation – ARM-based Embedded MPU

counting down on the slow clock divided by 8 from the MOSCXTCNT value. Since the MOSCXTCNT value is coded with
8 bits, the maximum startup time is about 62 ms.
When the counter reaches 0, the MOSCXTS bit is set, indicating that the main clock is valid. Setting the MOSCXTS bit in
PMC_IMR can trigger an interrupt to the processor.
21.6.7 Main Clock Oscillator Selection
The user can select either the 12 MHz Fast RC Oscillator or the 12 to 16 MHz Crystal Oscillator to be the source of Main
Clock.
The advantage of the 12 MHz Fast RC Oscillator is to have fast startup time, this is why it is selected by default (to start
up the system) and when entering in Wait Mode.
The advantage of the 12 to 16 MHz Crystal Oscillator is that it is very accurate.
The selection is made by writing the MOSCSEL bit in the Main Oscillator Register (CKGR_MOR). The switch of the Main
Clock source is glitch free, so there is no need to run out of SLCK, PLLACK or UPLLCK in order to change the selection.
The MOSCSELS bit of the Power Management Controller Status Register (PMC_SR) allows knowing when the switch
sequence is done.
Setting the MOSCSELS bit in PMC_IMR can trigger an interrupt to the processor.
21.6.8 Main Clock Frequency Counter
The device features a Main Clock frequency counter that provides the frequency of the Main Clock.
The Main Clock frequency counter is reset and starts incrementing at the Main Clock speed after the next rising edge of
the Slow Clock in the following cases:
 When the 12 MHz Fast RC Oscillator clock is selected as the source of Main Clock and when this oscillator
becomes stable (i.e., when the MOSCRCS bit is set)
 When the 12 to 16 MHz Crystal Oscillator is selected as the source of Main Clock and when this oscillator
becomes stable (i.e., when the MOSCXTS bit is set)
 When the Main Clock Oscillator selection is modified
Then, at the 16th falling edge of Slow Clock, the MAINFRDY bit in the Clock Generator Main Clock Frequency Register
(CKGR_MCFR) is set and the counter stops counting. Its value can be read in the MAINF field of CKGR_MCFR and
gives the number of Main Clock cycles during 16 periods of Slow Clock, so that the frequency of the 12 MHz Fast RC
Oscillator or 12 to 16 MHz Crystal Oscillator can be determined.
21.7
Divider and PLLA Block
The PLLA embeds an input divider to increase the accuracy of the resulting clock signals. However, the user must
respect the PLLA minimum input frequency when programming the divider.
Figure 21-6 shows the block diagram of the divider and PLLA block.
Figure 21-6. Divider and PLLA Block Diagram
DIVA
MULA OUTA
PLLADIV2
MAINCK
Divider
PLLA
/1 or /2
Divider
PLLACK
SLCK
PLLACOUNT
PLLA
Counter
LOCKA
SAM9G35 [DATASHEET]
11053E–ATARM–10-Mar-2014
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