SAM9G35_14 Datasheet, PDF (1217/1293 Pages) ATMEL Corporation – ARM-based Embedded MPU

45.7.97 Hardware Cursor Layer Control Register
Name:
LCDC_HCRCTRL
Address: 0xF8038364
Access:
Read-write
Reset:
0x00000000
31
30
29
28
–
–
–
–
23
22
21
20
–
–
–
–
15
14
13
12
–
–
–
–
7
6
5
4
–
–
DONEIEN
ADDIEN
27
–
19
–
11
–
3
DSCRIEN
• DFETCH: Transfer Descriptor Fetch Enable
0: Transfer Descriptor fetch is disabled.
1: Transfer Descriptor fetch is enabled.
• LFETCH: Lookup Table Fetch Enable
0: Lookup Table DMA fetch is disabled.
1: Lookup Tabled DMA fetch is enabled.
• DMAIEN: End of DMA Transfer Interrupt Enable
0: DMA transfer completed interrupt is enabled.
1: DMA transfer completed interrupt is disabled.
• DSCRIEN: Descriptor Loaded Interrupt Enable
0: Transfer descriptor loaded interrupt is enabled.
1: Transfer descriptor loaded interrupt is disabled.
• ADDIEN: Add Head Descriptor to Queue Interrupt Enable
0: Transfer descriptor added to queue interrupt is enabled.
1: Transfer descriptor added to queue interrupt is disabled.
• DONEIEN: End of List Interrupt Enable
0: End of list interrupt is disabled.
1: End of list interrupt is enabled.
26
–
18
–
10
–
2
DMAIEN
25
–
17
–
9
–
1
LFETCH
24
–
16
–
8
–
0
DFETCH
SAM9G35 [DATASHEET]
11053E–ATARM–10-Mar-2014
1217