SAM9G35_14 Datasheet, PDF (486/1293 Pages) ATMEL Corporation – ARM-based Embedded MPU

Multi-buffer Transfer with Linked List for Source and Linked List for Destination (Row 4)
1. Read the Channel Handler Status register to choose a free (disabled) channel.
2. Set up the chain of Linked List Items (otherwise known as buffer descriptors) in memory. Write the control informa-
tion in the LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx registers location of the buffer descriptor for each LLI in
memory (see Figure 31-6 on page 487) for channel x. For example, in the register, you can program the following:
1. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control
device by programming the FC of the DMAC_CTRLBx register.
2. Set up the transfer characteristics, such as:
 i. Transfer width for the source in the SRC_WIDTH field.
 ii. Transfer width for the destination in the DST_WIDTH field.
 iii. Source AHB master interface layer in the SIF field where source resides.
 iv. Destination AHB master interface layer in the DIF field where destination resides.
 v. Incrementing/decrementing or fixed address for source in SRC_INCR field.
 vi. Incrementing/decrementing or fixed address for destination DST_INCR field.
3. Write the channel configuration information into the DMAC_CFGx register for channel x.
1. Designate the handshaking interface type (hardware or software) for the source and destination peripherals.
This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits,
respectively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination
requests for the specific channel. Writing a ‘0’ activates the software handshaking interface to handle
source/destination requests.
2. If the hardware handshaking interface is activated for the source or destination peripheral, assign the hand-
shaking interface to the source and destination peripheral. This requires programming the SRC_PER and
DST_PER bits, respectively.
4. Make sure that the LLI.DMAC_CTRLBx register locations of all LLI entries in memory (except the last) are set as
shown in Row 4 of Table 31-3 on page 483. The LLI.DMAC_CTRLBx register of the last Linked List Item must be
set as described in Row 1 of Table 31-3. Figure 31-5 on page 482 shows a Linked List example with two list items.
5. Make sure that the LLI.DMAC_DSCRx register locations of all LLI entries in memory (except the last) are non-zero
and point to the base address of the next Linked List Item.
6. Make sure that the LLI.DMAC_SADDRx/LLI.DMAC_DADDRx register locations of all LLI entries in memory point
to the start source/destination buffer address preceding that LLI fetch.
7. Make sure that the LLI.DMAC_CTRLAx.DONE field of the LLI.DMAC_CTRLAx register locations of all LLI entries
in memory are cleared.
8. If source Picture-in-Picture mode is enabled (DMAC_CTRLBx.SRC_PIP is enabled), program the DMAC_SPIPx
register for channel x.
9. If destination Picture-in-Picture is enabled (DMAC_CTRLBx.DST_PIP is enabled), program the DMAC_DPIPx
register for channel x.
10. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the status register:
DMAC_EBCISR.
11. Program the DMAC_CTRLBx, DMAC_CFGx registers according to Row 4 as shown in Table 31-3 on page 483.
12. Program the DMAC_DSCRx register with DMAC_DSCRx(0), the pointer to the first Linked List item.
13. Finally, enable the channel by writing a ‘1’ to the DMAC_CHER.ENAx bit, where x is the channel number. The
transfer is performed.
14. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0).
Note:
The LLI.DMAC_SADDRx, LLI. DMAC_DADDRx, LLI.DMAC_DSCRx, LLI.DMAC_CTRLAx and
LLI.DMAC_CTRLBx registers are fetched. The DMAC automatically reprograms the DMAC_SADDRx,
DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLBx and DMAC_CTRLAx channel registers from the
DMAC_DSCRx(0).
SAM9G35 [DATASHEET]
11053E–ATARM–10-Mar-2014
486