SAM9G35_14 Datasheet, PDF (397/1293 Pages) ATMEL Corporation – ARM-based Embedded MPU

Figure 29-14.WRITE_MODE = 1. The write operation is controlled by NWE
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NWE,
NWR0, NWR1,
NWR2, NWR3
NCS
D[31:0]
29.9.4.2 Write is Controlled by NCS (WRITE_MODE = 0)
Figure 29-15 shows the waveforms of a write operation with WRITE_MODE set to 0. The data is put on the bus during
the pulse and hold steps of the NCS signal. The internal data buffers are switched to output mode after the
NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE.
Figure 29-15.WRITE_MODE = 0. The write operation is controlled by NCS
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NWE,
NWR0, NWR1,
NWR2, NWR3
NCS
D[31:0]
SAM9G35 [DATASHEET]
11053E–ATARM–10-Mar-2014
397