AT91SAM9R64_1 Datasheet, PDF (754/903 Pages) ATMEL Corporation – AT91 ARM Thumb Microcontrollers

41.4.9
Speed Identification
The high speed reset is managed by the hardware.
At the connection, the host makes a reset which could be a classic reset (full speed) or a high
speed reset.
At the end of the reset process (full or high), the ENDRESET interrupt is generated.
Then the CPU should read the SPEED bit in UDPHS_INTSTAx to ascertain the speed mode of
the device.
41.4.10
USB V2.0 High Speed Global Interrupt
Interrupts are defined in Section 41.5.3 ”UDPHS Interrupt Enable Register” (UDPHS_IEN) and
in Section 41.5.4 ”UDPHS Interrupt Status Register” (UDPHS_INTSTA).
41.4.11
Endpoint Interrupts
Interrupts are enabled in UDPHS_IEN (see Section 41.5.3 ”UDPHS Interrupt Enable Register”)
and individually masked in UDPHS_EPTCTLENBx (see Section 41.5.17 ”UDPHS Endpoint
Control Enable Register”).
.
Table 41-4. Endpoint Interrupt Source Masks
SHRT_PCKT
Short Packet Interrupt
BUSY_BANK
Busy Bank Interrupt
NAK_OUT
NAKOUT Interrupt
NAK_IN/ERR_FLUSH
NAKIN/Error Flush Interrupt
STALL_SNT/ERR_CRISO/ERR_NB_TRA
Stall Sent/CRC error/Number of Transaction Error
Interrupt
RX_SETUP/ERR_FL_ISO
Received SETUP/Error Flow Interrupt
TX_PK_RD /ERR_TRANS
TX Packet Read/Transaction Error Interrupt
TX_COMPLT
Transmitted IN Data Complete Interrupt
RX_BK_RDY
Received OUT Data Interrupt
ERR_OVFLW
Overflow Error Interrupt
MDATA_RX
MDATA Interrupt
DATAX_RX
DATAx Interrupt
754 AT91SAM9R64/RL64 Preliminary
6289C–ATARM–28-May-09