AT91SAM9R64_1 Datasheet, PDF (223/903 Pages) ATMEL Corporation – AT91 ARM Thumb Microcontrollers

AT91SAM9R64/RL64 Preliminary
23.6.4 SDRAMC Low Power Register
Register Name:
SDRAMC_LPR
Access Type:
Read/Write
Reset Value:
0x0
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
–
–
TIMEOUT
DS
9
8
TCSR
7
6
5
4
3
2
1
0
–
PASR
–
–
LPCB
• LPCB: Low-power Configuration Bits
00
Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the
SDRAM device.
The SDRAM Controller issues a Self-refresh command to the SDRAM device, the SDCLK clock is deactivated
01
and the SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when accessed and enters
it after the access.
The SDRAM Controller issues a Power-down Command to the SDRAM device after each access, the SDCKE
10
signal is set to low. The SDRAM device leaves the Power-down Mode when accessed and enters it after the
access.
11
The SDRAM Controller issues a Deep Power-down command to the SDRAM device. This mode is unique to
low-power SDRAM.
• PASR: Partial Array Self-refresh (only for low-power SDRAM)
PASR parameter is transmitted to the SDRAM during initialization to specify whether only one quarter, one half or all banks
of the SDRAM array are enabled. Disabled banks are not refreshed in self-refresh mode. This parameter must be set
according to the SDRAM device specification.
After initialization, as soon as PASR field is modified and self-refresh mode is activated, the Extended Mode Register is
accessed automatically and PASR bits are updated before entry in self-refresh mode.
• TCSR: Temperature Compensated Self-Refresh (only for low-power SDRAM)
TCSR parameter is transmitted to the SDRAM during initialization to set the refresh interval during self-refresh mode
depending on the temperature of the low-power SDRAM. This parameter must be set according to the SDRAM device
specification.
After initialization, as soon as TCSR field is modified and self-refresh mode is activated, the Extended Mode Register is
accessed automatically and TCSR bits are updated before entry in self-refresh mode.
• DS: Drive Strength (only for low-power SDRAM)
DS parameter is transmitted to the SDRAM during initialization to select the SDRAM strength of data output. This parame-
ter must be set according to the SDRAM device specification.
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