AT91SAM9R64_1 Datasheet, PDF (229/903 Pages) ATMEL Corporation – AT91 ARM Thumb Microcontrollers

AT91SAM9R64/RL64 Preliminary
24. Error Corrected Code (ECC) Controller
24.1 Description
NAND Flash/SmartMedia devices contain by default invalid blocks which have one or more
invalid bits. Over the NAND Flash/SmartMedia lifetime, additional invalid blocks may occur
which can be detected/corrected by ECC code.
The ECC Controller is a mechanism that encodes data in a manner that makes possible the
identification and correction of certain errors in data. The ECC controller is capable of single bit
error correction and 2-bit random detection. When NAND Flash/SmartMedia have more than 2
bits of errors, the data cannot be corrected.
The ECC user interface is compliant with the ARM Advanced Peripheral Bus (APB rev2).
24.2 Block Diagram
Figure 24-1. Block Diagram
Static
Memory
Controller
NAND Flash
SmartMedia
Logic
ECC
Controller
Ctrl/ECC Algorithm
User Interface
APB
24.3
Functional Description
A page in NAND Flash and SmartMedia memories contains an area for main data and an addi-
tional area used for redundancy (ECC). The page is organized in 8-bit or 16-bit words. The page
size corresponds to the number of words in the main area plus the number of words in the extra
area used for redundancy.
6289C–ATARM–28-May-09
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