AT91SAM9R64_1 Datasheet, PDF (280/903 Pages) ATMEL Corporation – AT91 ARM Thumb Microcontrollers

27.8.10 PMC Clock Generator PLL Register
Name:
CKGR_PLLR
Acess:
Read-write
31
30
29
28
27
26
25
24
–
–
1
–
–
MUL
23
22
21
20
19
18
17
16
MUL
15
14
13
12
11
10
9
8
OUT
PLLCOUNT
7
6
5
4
3
2
1
0
DIV
Possible limitations on PLL input frequencies and multiplier factors should be checked before using the PMC.
Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLR register.
• DIV: Divider
DIV
0
1
2 - 255
Divider Selected
Divider output is 0
Divider is bypassed
Divider output is the selected clock divided by DIV.
• PLLCOUNT: PLL Counter
Specifies the number of slow clock cycles before the LOCK bit is set in PMC_SR after CKGR_PLLR is written.
• OUT: PLL Clock Frequency Range
To optimize clock performance, this field must be programmed as specified in “PLL Characteristics” in the Electrical Char-
acteristics section of the product datasheet.
• MUL: PLL Multiplier
0 = The PLL is deactivated.
1 up to 2047 = The PLL Clock frequency is the PLL input frequency multiplied by MUL+ 1.
280 AT91SAM9R64/RL64 Preliminary
6289C–ATARM–28-May-09