AT91SAM9R64_1 Datasheet, PDF (588/903 Pages) ATMEL Corporation – AT91 ARM Thumb Microcontrollers

AT91SAM9R64/RL64 Preliminary
– Source AHB master interface layer in the SIF field where source resides.
– Destination AHB master interface master layer in the DIF field where destination
resides.
– Incrementing/decrementing or fixed address for source in SRC_INCR field.
– Incrementing/decrementing or fixed address for destination in DST_INCR field.
e. If source picture-in-picture is enabled (DMAC_CTRLBx.SPIP is enabled), program
the DMAC_SPIPx register for channel x.
f. If destination picture-in-picture is enabled (DMAC_CTRLBx.DPIP), program the
DMAC_DPIPx register for channel x.
g. Write the channel configuration information into the DMAC_CFGx register for chan-
nel x.
4. After the DMAC channel has been programmed, enable the channel by writing a ‘1’ to
the DMAC_CHER.ENABLE[n] bit where n is the channel number. Make sure that bit 0
of the DMAC_EN.ENABLE register is enabled.
5. When the buffer transfer has completed, the DMAC reloads the DMAC_SADDRx regis-
ter. The DMAC_DADDRx register remains unchanged. Hardware sets the buffer
complete interrupt. The DMAC then samples the row number as shown in Table 37-1
on page 575. If the DMAC is in Row 1, then the DMAC transfer has completed. Hard-
ware sets the transfer complete interrupt and disables the channel. So you can either
respond to the Buffer Complete or Transfer Complete interrupts, or poll for ENABLE
field in the Channel Status Register (DMAC_CHSR.ENABLE[n] bit) until it is cleared by
hardware, to detect when the transfer is complete. If the DMAC is not in Row 1, the next
step is performed.
6. The DMAC transfer proceeds as follows:
a. If the buffer complete interrupt is un-masked (DMAC_EBCIMR.BTC[x] = ‘1’, where
x is the channel number) hardware sets the buffer complete interrupt when the buf-
fer transfer has completed. It then stalls until STALLED[n] bit of DMAC_CHSR is
cleared by writing in the KEEPON[n] field of DMAC_CHER register where n is the
channel number. If the next buffer is to be the last buffer in the DMAC transfer, then
the buffer complete ISR (interrupt service routine) should clear the automatic mode
bit, DMAC_CTRLBx.AUTO. This puts the DMAC into Row 1 as shown in Table 37-
1 on page 575. If the next buffer is not the last buffer in the DMAC transfer then the
automatic transfer mode bit should remain enabled to keep the DMAC in Row 11 as
shown in Table 37-1 on page 575.
b. If the buffer complete interrupt is masked (DMAC_EBCIMR.BTC[x] = ‘1’, where x is
the channel number) then hardware does not stall until it detects a write to the buf-
fer transfer completed interrupt enable register but starts the next buffer transfer
immediately. In this case software must clear the automatic mode bit,
DMAC_CTRLBx.AUTO, to put the device into ROW 1 of Table 37-1 on page 575
before the last buffer of the DMAC transfer has completed.
The transfer is similar to that shown in Figure 37-12 on page 589.
The DMAC Transfer flow is shown in Figure 37-13 on page 590.
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