AT32AP7001_1 Datasheet, PDF (750/829 Pages) ATMEL Corporation – AVR32 32-bit Microcontroller

AT32AP7001
35.6.1 ISI Control 1 Register
Register Name: CR1
Access Type: Read/Write
Reset Value: 0x00000002
31
30
29
28
27
26
25
24
SFD
23
22
21
20
19
18
17
16
SLD
15
14
13
12
11
CODEC_EN
THMASK
FULL
-
10
9
8
FRATE
7
CRC_SYNC
6
EMB_SYNC
5
4
3
2
1
-
PIXCLK_POL VSYNC_POL HSYNC_POL
DIS
0
RST
• RST: Image sensor interface reset
0: No action
1: Resets the image sensor interface.
• DIS: Image sensor disable:
0: Enable the image sensor interface.
1: Finish capturing the current frame and then shut down the module.
• HSYNC_POL: Horizontal synchronization polarity
0: HSYNC active high
1: HSYNC active low
• VSYNC_POL: Vertical synchronization polarity
0: VSYNC active high
1: VSYNC active low
• PIXCLK_POL: Pixel clock polarity
0: Data is sampled on rising edge of pixel clock
1: Data is sampled on falling edge of pixel clock
• EMB_SYNC: Embedded synchronization
0: Synchronization by HSYNC, VSYNC
1: Synchronization by embedded synchronization sequence SAV/EAV
• CRC_SYNC: Embedded synchronization
0: No CRC correction is performed on embedded synchronization
1: CRC correction is performed. if the correction is not possible, the current frame is discarded and the CRC_ERR is set in
the status register.
• FRATE: Frame rate [0..7]
0: All the frames are captured, else one frame every FRATE+1 is captured.
32015G–AVR32–09/09
750